Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications

Dublin Core

Title

Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications

Subject

Adiabatic Logic
Full Adder
ECRL
2PASCL
Ripple Carry Adder(RCA)
Carry Select Adder(CSLA)
Carry Save Adder(CSA)
Carry Skip Adder(CSA)
Brent Kung Adder(BKA).

Description

In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL styles. Moreover in this paper, 32 bit adders such as Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Skip Adder (CSKA) and Brent Kung Adder (BKA) are realised using proposed ECRL and 2PASCL adiabatic full adders. All the adders are implemented and simulated using TANNER EDA tool 22nm technology, parameters like power, area, delay and power delay product (PDP) of all the adders are observed at different operating frequencies, with supply voltage of 0.95 v and load capacitance of 0.5 pF. The observed parameters are compared with the existing adiabatic full adder designs and concluded that the proposed adiabatic full adders have the advantages of less power, delay and transistor count. In conclusion ECRL full adder is 31% faster, has equal PDP and less area than 2PASCL full adder. At 1000MHz ECRL 32 bit carry save adder is having less delay among all the 32 bit adder and 65% less PDP than 2PASCL adder and it is concluded that ECRL 32 bit carry save adder can be selected for implementation of circuits that can be used in portable mobile applications.

Creator

Suguna, T.
Janaki Rani, M.

Source

International Journal of Interactive Mobile Technologies (iJIM); Vol. 14 No. 05 (2020); pp. 73-94
1865-7923

Publisher

International Association of Online Engineering (IAOE), Vienna, Austria

Date

2020-04-07

Rights

Copyright (c) 2020 T. Suguna, M. Janaki Rani

Relation

Format

application/pdf

Language

eng

Type

info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Peer-reviewed Article

Identifier

Citation

T Suguna. and Janaki Rani, M., Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications, International Association of Online Engineering (IAOE), Vienna, Austria, 2020, accessed November 24, 2024, https://igi.indrastra.com/items/show/1659

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